A delta-sigma modulator is widely used in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). In this specification, an ADC which uses delta-sigma modulation and a DAC which uses delta-sigma modulation are referred to as a delta-sigma ADC and a delta-sigma DAC, respectively. A delta-sigma modulator may be called a sigma-delta modulator. A delta-sigma modulator can spread quantization error (or quantization noise) power to an oversampling frequency fosr by oversampling. A delta-sigma modulator also can shift quantization noise to a higher frequency domain owing to noise shaping characteristics thereof, thereby suppressing quantization noise in the frequency band of interest (typically, a frequency band lower than the Nyquist frequency).
However, continuous-time delta-sigma modulators and continuous-time delta-sigma DACs are known to have low clock jitter tolerance. This is because the noise transfer function (NTF) of a delta-sigma modulator has a peak at half the oversampling frequency fosr (i.e., fosr/2). Since the out-of-band quantization noise (in particular, the quantization noise near fosr/2) is folded back into the frequency band of interest due to interference caused by clock jitter, the noise characteristics of the delta-sigma modulator are degraded.
Hezar et al., “A 110 dB SNR and 0.5 mW Current-Steering Audio DAC Implemented in 45 nm CMOS”, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp 304-305, 7-11 Feb. 2010 (hereinafter “Hezar et al.”) and U.S. Patent Application Publication No. 2011/0043398, filed by Hezar et al., entitled “Cascaded DAC Architecture with Pulse Width Modulation” (hereinafter “U.S. Patent Application Publication No. 2011/0043398”) disclose delta-sigma DACs including an analog finite impulse response (AFIR) filter DAC which is coupled to the output of a delta-sigma modulator (i.e., noise shaping circuit) (see FIGS. 16.7.2 and 16.7.3 of Hezar et al. and FIGS. 6, 7 and 9 of U.S. Patent Application Publication No. 2011/0043398). The AFIR filter DAC has an AFIR filter, and each tap of this AFIR filter includes a multi-bit or 1-bit DAC. Typically, a DAC disposed on each tap is a current-steering DAC. The analog outputs of the multiple DACs are summed up to form an analog output signal. That is, the DACs disclosed in Hezar et al. and U.S. Patent Application Publication No. 2011/0043398 are configured to calculate a moving sum of the output of the delta-sigma modulator in the AFIR filter DAC. This configuration can suppress the out-of-band quantization noise (see paragraphs 0030 and 0031 and FIG. 6 of U.S. Patent Application Publication No. 2011/0043398). Thus, it is possible to reduce the degradation of noise characteristics caused when the out-of-band quantization noise is folded back into the frequency band of interest due to interference caused by clock jitter.
As described above, the delta-sigma DACs disclosed in Hezar et al. and Patent Application Publication No. 2011/0043398 are configured to calculate a moving sum of the output of the delta-sigma modulator in the AFIR filter DAC which is coupled to the output of the delta-sigma modulator. This configuration requires the same number of DACs as the number of taps of the AFIR filter. However, disposition of many DACs unfavorably increases the circuit size. For a delta-sigma DAC, it may calculate a moving sum of the output of the delta-sigma modulator in the digital domain rather than in the analog domain. However, digital calculation of a moving sum refers to digital addition and therefore the bit number of a digital signal is increased after the moving sum is calculated. This increases the number of devices of analog circuits including DACs. Further, a dynamic element matching (DEM) circuit may be required for correcting mismatch of the analog circuit. In this case, an additional logic circuit may be required.
For a delta-sigma ADC, a moving sum of the output of the delta-sigma modulator can be calculated in the digital domain. Typically, one DAC is disposed on a feedback path in the delta-sigma modulator to feed back the output signal of the quantizer. If a delta-sigma ADC employs a configuration where a moving sum of the output of the delta-sigma modulator is fed back to the input of an integrator in the delta-sigma modulator, multiple DACs must be disposed on the feedback path. This may increase the circuit size.
On the other hand, if a delta-sigma ADC employs a configuration where the output of the quantizer prior to calculating a moving sum is fed back to the input of the integrator, any increase in the circuit size resulting from the disposition of many feedback DACs on the feedback path does not occur. However, this configuration fails to filter the quantization noise which is fed back from the output of the quantizer to the input of the integrator. For this reason, this configuration may not sufficiently suppress the degradation of noise characteristics caused when the out-of-band quantization noise is folded back into the frequency band of interest.